182 ps7044g 06/02/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c1201 functional block diagram features ? supports laser printer pixel rates up to 40 mhz. 70 mhz for ?c? speed version. ? jitter less than 300ps. ? easily programmable frequency selections via parallel interface. post divider (r) designed to load only during the beam detect interval. ? source clock input can be from crystal or oscillator. ? source clock rates from 8 mhz up to 22 mhz (from crystal or oscillator). ? active low asynchronous reset input for synchronization with engine via beam detect input. ? synchronized beam detect output to support external state machines. ? glitch-less clock output after beam detect. ? supports dynamic frequency changes on a line-per-line basis. ? mixed line resolution supports half-toning and gray scale operations. ? minimizes controller memory utilization (low-resolution text mixed with high-resolution images). ? on-chip vco loop filter (no external components). ? on-chip crystal oscillator (modified pierce). ? single 5v power supply. ? low power consumption. ? 20-pin wide body (300-mil) soic package (s) precision clock generator for laser printers description the pi6c1201 is an advanced cmos clock generator designed specifically to support pixel clock generation in low-cost laser printers. capable of generating highly stable clock frequencies up to 70 mhz, this device supports printer engines with dot resolutions of 1,200 dpi and above. page speeds may range from 4 pages per minute to better than 60 pages per minute. mixed-line resolution supports half-toning and gray scale opera- tions (low-resolution text mixed with high-resolution images) and minimizes controller memory utilization 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 bdowid gnd pclk gnd bd# bdout bdopol r0 r1 r2 x1/iclk x2 sel0 gnd sel1 sel2 v cc agnd oe av cc pinout diagram 20-pin s bd# oe bdout pclk r0 r1 r2 control & resolution select (r) idac logic n . . vco loop filter charge pump phase & freq det clk in 2 . . x1 x2 prescale multiplier 012 sel
pi6c1201 precision clock generator for laser printers 183 ps7044g 06/02/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pin description pin name description 1 x1/iclk crystal, or input from external clock source . this pin is connected to a crystal or may be used to input an external reference frequency. when connected to a crystal, a 33 pf (typ) capacitor should be connected from this pin to ground. when driven by an external clock there is no need for a capacitor. 2 x2 crystal. output of ring oscillator. this pin should typically have a 22 pf capacitor to ground when used with a crystal. for fine-tuning the crystal frequency, this capacitor can be trimmed from 15 pf to 33 pf. if x1 is driven by an external clock source, there is no need for a capacitor. 4 gnd digital ground 3, 5, 6 sel(0-2) selects vco/crystal multiplication ratio . these pins can be dynamically changed anytime (not recommended during active imaging). these inputs must be tied high/low or driven actively to guarantee that the setting stays valid. refer to table 2 for additional information. these pins have internal pull-up resistors. 7v cc digital vcc 8 agnd analog ground 9 oe output enable . when pulled high, this pin will enable the pclk and the bdout outputs. when pulled low, these pins are tri-stated. this pin has an internal pull-up resistor. 10 av cc analog vcc 11, r(0-2) output resolution selection . used to set the final dot resolution. the divide ratios set by these pins 12, 13 are all tightly aligned synchronous outputs designed to eliminate glitches and allow dynamic changes to the output clock dot resolution frequency on a per-line basis. these pins can only be changed during the bd# (beam detect) active interval. the signals should be externally latched at least one or two pclk cycles prior to bd# going active to guarantee internal latches setup and hold times. r0 allows single-pin control for 1/4 or 1/8 mode (assuming r1 and r2 = 1). please refer to table 1 for further information. these pins have internal pull-up resistors. 14 bdopol beam detect output polarity: this pin is used to set the polarity of the bdout output (pin 15). when this pin is low, the bdout polarity is active high. when this pin is high, the bdout polarity is active low. this pin is pulled up internally. 15 bdout beam detect output . this pin signals the start of a new line after synchronization has occurred. the bdout signal will go active when the incoming bd# signal is detected and synchronized. the width of this pulse is dependent upon the vco frequency and the current pclk setting. please refer to the timing diagram for additional information. the polarity of bdout can be controlled by bdopol (pin 14) and the width can be set to 1 or 2 pclks by bdowid (pin20). bdout can be tri-stated by the oe pin. bdout has a 12ma balanced drive cmos output. 16 bd# beam detect input from engine . the engine signal that drives this pin indicates that the end (or beginning) of a line has been detected. since this signal is typically an asynchronous strobe, this active- low edge-sensitive input is extremely metastable-resistant. this input has a ttl-compatible input threshold with hysteresis. this pin has an internal pull-up resistor. 17 gnd digital ground 18 pclk pixel clock output . the output frequency of this pin is a function of the crystal (or input clock) frequency (pre-scaled to ? 2), the multiply ratio as set by sel(0-2) and the final divide ratio as set by r(0-2): pclk = crystal x (1/2) x [32, 16, or 8 as defined by sel(0-1)] x (1/8 or 1/4 as controlled by r0 - assumes r1=r2=1). this output can be glitchlessly synchronized to an external asynchronous event by asserting the bd# input. the minimum indeterminacy of the alignment to the external event is controlled by the width of the vco clock. please refer to timing diagrams for additional information. the pclk output can be tri-stated by the oe pin. this pin has a 12ma balanced-drive cmos output. 19 gnd digital ground 20 bdowid beam detect output width: this pin is used to set the width of the bdout output (pin 15). when this pin is low, the bdout width is two pclk periods. when this pin is high, the bdout width is one pclk period. this pin has an internal pull-up resistor.
184 ps7044g 06/02/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c1201 precision clock generator for laser printers basic pll flow diagram table 1. dot resolution divider pin setting table 2. vco multiplier pin setting note: 1. the relationship of the vco to pclk is controlled by the r synchronous divider. for example: (a) 1 pclk = 4 vco clocks if r0 = 0 & r1 = r2 = 1 (b) 1 pclk = 8 vco clocks if r0 = 1 & r1 = r2 = 1 2 r1 r0 rn o i t c n u fr 000 ? 6 1 6 1 001 ? 2 3 2 3 010 ? 4 6 4 6 011 ? 8 2 1 8 2 1 100 ? 6 5 2 6 5 2 10 1 ? 2 2 110 ? 4 4 111 ? 8 8 2 l e s1 l e s0 l e sn o i t c n u f 10 0 d e v r e s e r 10 1 8 x 110 2 3 x 111 6 1 x pclk bdout r0 r1 r2 synchronous counter/divider dot resolution 2 . . prescaler divider 012 sel vco/multiplier 2to . . . . 256 x8, x16, x32 xtal bd#
pi6c1201 precision clock generator for laser printers 185 ps7044g 06/02/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 dc electrical characteristics (v cc = 5v 10% for blank and a speed, vcc = 5v 5% for c speed. t a = 0 c to 70 c) notes: 1. these parameters are guaranteed by design and measured at characterization only. 2. for max. or min. conditions, use appropriate values specified under electrical characteristics for the appropriate device typ e. 3. typical values are shown at vcc = 5.0v, +25c ambient and maximum loading. 4. not more than one output should be shorted at one time. duration of test should not exceed one second. 5. c speed operation is limited to a 5% vcc tolerance l o b m y sn o i t p i r c s e ds n o i t i d n o c t s e t ) 2 ( . n i m. p y t ) 3 ( . x a ms t i n u v ih ) 1 ( e g a t l o v h g i h t u p n i# d b & 1 x t p e c x e s t u p n i l l a0 . 2 ?? v v ih 1 x ) 1 ( 1 x e g a t l o v h g i h t u p n it u p n i 1 x0 . 1 - c c v ?? v bdth ) 1 ( e g a t l o v d l o h s e r h t t u p n i# d bv cc = v 5 . 5 o t v 5 . 42 . 1 ? 4 . 1 v il ) 1 ( e g a t l o v w o l t u p n is t u p n i l l a ?? 8 . 0 i ih t n e r r u c h g i h t u p n i- l l u p h t i w p u 1 x t p e c x e s t u p n i l l a v cc v , . x a m = in v = cc ?? 5 m a i il t n e r r u c w o l t u p n i- l l u p h t i w p u , 1 x t p e c x e s t u p n i l l a v cc v , . x a m = in v 0 = - 0 5 ?? i ih 1 x1 x t n e r r u c h g i h t u p n iv , t u p n i 1 x cc . x a m = v in v = cc ?? 0 5 1 i il 1 x1 x t n e r r u c w o l t u p n iv , t u p n i 1 x cc . x a m = v in v 0 = - 0 5 1 ?? v oh e g a t l o v h g i h t u p t u o2 x t p e c x e s t u p t u o l l a v cc i , . n i m = oh = - a m 2 1 4 . 2 ?? v v ol e g a t l o v w o l t u p t u o, 2 x t p e c x e s t u p t u o l l a v cc i , . n i m = ol a m 2 1 + = ?? 4 . 0 i os ) 4 , 1 ( t n e r r u c t i u c r i c t r o h sv cc v 5 2 . 5 = v out d n g = 5 2 ?? a m i c 0 6 1 t n e r r u c y l p p u s c i m a n y dv cc z h m 0 2 = 1 x , v 0 . 5 = 6 1 x = l e s ?? 5 3 i c 0 4 2 t n e r r u c y l p p u s c i m a n y d ) y l n o a 1 0 2 1 c 6 r o f ( v cc z h m 5 1 = 1 x , v 0 . 5 = 2 3 x = l e s ?? 0 5 i c 0 8 2 ) 5 ( t n e r r u c y l p p u s c i m a n y d ) y l n o c 1 0 2 1 c 6 r o f ( v cc , z h m 5 . 7 1 = 1 x , v 0 . 5 = 2 3 x = l e s ?? 0 6 maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. storage temperature ................................................................. C65c to +150c ambient temperature with power applied .................................... 0c to +70c supply voltage to ground potential (inputs & vcc only) ........... C0.3v to +7.0v dc input voltage ......................................................................... C0.5v to +7.0v dc output current ................................................................................... 120 ma power dissipation ........................................................................................ 1.0 w
186 ps7044g 06/02/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c1201 precision clock generator for laser printers switching characteristics vcc = 5v 10% for blank and a speed, vcc = 5v 5% for c speed. t a = 0o c to 70o c notes: 1. these parameters are guaranteed by design and measured at characterization only. 2. the vco frequency can be determined by the following formula: n = vco multiplier value. see table 2 for example: for x1 = 20 mhz and sel = x16, then: fvco = (20 mhz / 2) x 16 = 160 mhz for x1 = 15 mhz and sel = x32, then: fvco = (15 mhz / 2) x 32 = 240 mhz 3. the vco clock period is determined by the formula: t vco = 1 / f vco . for design aid only. 4. t pclk = t vco x r, r = output dot resolution divider function (see table 1). for design aid only. not subject to production testing. l o b m y sn o i t p i r c s e ds n o i t i d n o c t s e t. n i m. p y t. x a ms t i n u r t ) 1 ( ) v 0 . 2 o t v 8 . 0 ( e m i t e s i r t u p t u o k l c p f p 0 3 = l c 2 s n tf ) 1 ( ) v 8 . 0 o t v 0 . 2 ( e m i t l l a f t u p t u o k l c p 2 h z p t ) 1 ( l z p t ) 1 ( e m i t e l b a n e t u p t u o k l c p o t e o ) m r o f e v a w & t i u c r i c t s e t e h t o t r e f e r e s a e l p ( 0 0 5 = l r , f p 0 3 = l c w 0 0 5 = u p r w v 7 o t ) y l n o z l p t d n a l z p t r o f ( 5 . 15 . 7 z h p t ) 1 ( z l p t ) 1 ( e m i t e l b a s i d t u p t u o k l c p o t e o ) m r o f e v a w & t i u c r i c t s e t e h t o t r e f e r e s a e l p ( 5 . 10 . 6 t d ) 1 ( e l c y c y t u d k l c p 0 5 / 0 55 5 / 5 4% fn i l a t x y c n e u q e r f t u p n i l a t s y r c ) z h m 0 . 5 1 t a d e t s e t n o i t c u d o r p ( o c v g n i w o l l o f e h t n i h t i w : e g n a r y c n e u q e r f 8 2 2 z h m fn i y c n e u q e r f t u p n i n e v i r d ) z h m 0 3 d n a , 2 2 , 0 2 , 4 t a d e t s e t n o i t c u d o r p ( 8 2 2 fo c v ) 2 ( ) z h m 0 4 = k l c p . x a m ( y c n e u q e r f o c v e d a r g d e e p s " k n a l b "0 2 16 7 1 fo c v ) 2 ( e d a r g d e e p s " a "0 2 10 4 2 fo c v ) 2 ( ) z h m 0 7 = k l c p . x a m ( y c n e u q e r f o c v) c c v % 5 ( e d a r g d e e p s " c "0 2 10 8 2 s i j t ) 1 ( r e t t i j a m g i s e n o k l c p , z h m 5 1 = 1 x 8 = r , 2 3 x = l e s 0 5 s p b a j t ) 1 ( r e t t i j k a e p - o t - k a e p m r e t t r o h s k l c p 0 0 3 o c v t ) 3 ( d o i r e p k c o l c o c v 1 7 5 . 3 3 3 3 . 8 s n tk l c p ) 4 ( d o i r e p k c o l c k l c p pulse generator v in d.u.t. v out +7v rt cl 30pf rl 500 bench characterization test circuit w 500 w test open drain disable low enable low all other inputs switch closed open rpu cl = load capacitance includes jig and probe capacitance rl = load resistance rt = termination resistance should be equal to zout of pulse generator rpu = pull-up resistance bench characterization waveform enable and disable timing oe output normally high output normally low enable disable tpzl tpzh 1.5v 3.5v 3v 0v 0v 3.5v 1.5v 0.3v 0.3v tphz tplz 1.5v 0v voh vol pulse generator for all pulses: rate 1.0mhz; zout 50 w , tf, tr 2.5ns 1.5v f xtalin or f in 2 f vco = x n
pi6c1201 precision clock generator for laser printers 187 ps7044g 06/02/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 timing table (4) vcc = 5v 10% for blank and a speed, vcc = 5v 5% for c speed. t a = 0o c to 70o c . m y sn o i t p i r c s e d. n i m. p y t. x a m 1 th t d i w e s l u p # d b m u m i n i m ) 2 ( o c v t 2 2 2 t ) 1 ( c n y s d b o t e v i t c a # d b m o r f e m i to c v t 8 1o c v t 9 1 3 t o t # d b m o r f e m i t s u o n o r h c n y s t u o d b k l c p t 5 . 0 + o c v t 9 1 t + d 3 t j t 5 . 0 - k l c p t 5 . 0 + o c v t 0 2 t + d 3 t j t 5 . 0 + 4 t ) 1 ( 0 = d i w o d b e s l u p t u o d b f o h t d i w 1 = d i w o d b 4 t j t 5 . 0 - k l c p t 2 4 t j t 5 . 0 - k l c p t 1 k l c p t 2 k l c p t 1 4 t j t 5 . 0 + k l c p t 2 4 t j t 5 . 0 + k l c p t 1 5 t t s r i f e h t o t e v i t c a t u o d b m o r f e m i t k l c p f o e g d e g n i s i r d i l a v 5 t j t 5 . 0 - k l c p t 7 4 . 0 5 . 0 k l c p t 5 t j t 5 . 0 + k l c p t 5 . 0 6 t t s r i f e h t o t e v i t c a # d b m o r f e m i t l a t o t k l c p f o e g d e g n i s i r d i l a v t 9 1 = 5 t + 3 to c v ++ k l c p t 7 9 . 0t d 6 t j t 5 . 0 C o c v t 0 2 = 5 t + 3 t t + k l c p t 0 . 1 + d 5 . 0 + 6 t j t t d s y a l e d r e f f u b l a t o t p i h c - n o3 e t o n e e s3 e t o n e e s 3 t j t ) 5 ( r e t t i j k a e p - o t - k a e p 3 ts p 0s p 0 0 3 4 t j t ) 5 ( r e t t i j k a e p - o t - k a e p 4 ts p 0s p 0 0 3 5 t j t ) 5 ( r e t t i j k a e p - o t - k a e p 5 ts p 0s p 0 0 3 6 t j t ) 5 ( r e t t i j k a e p - o t - k a e p 6 ts p 0s p 0 0 3 notes: 1. these parameters are guaranteed by design and functional test only. 2. the width of the bd# pulse (t1) must meet the minimum width requirements of 22 t vco . bd# pulses less than 22 t vco will not achieve synchronization and will not generate bdout. for measurement purposes, the falling edge of bd# should be 6 ns or less. 3. t d is extracted from initial product characterization. it varies with both vcc and temperature. the following linear regression f ormulas may be used to calculate t d for 4.5v < vcc < 5.5v and 0 o c < t a < 70 o c. this is provided for design purposes only. a +10% guardband of the calculated value will be used for production testing. a. linear regression of t d vs. vcc at a fixed temperature: t d = slope x vcc + intercept e r u t a r e p m e t ( o ) c 00 20 40 60 8 ) s n ( t p e c r e t n i2 3 0 . 4 16 5 7 . 4 15 8 5 . 5 11 7 7 . 6 17 0 1 . 7 1 ) v / s n ( e p o l s4 2 2 . 1 -6 9 2 . 1 -6 9 3 . 1 -8 6 5 . 1 -4 6 5 . 1 - ) v ( c c v0 5 . 45 7 . 40 0 . 55 2 . 50 5 . 5 ) s n ( t p e c r e t n i8 7 5 . 86 0 2 . 82 7 8 . 76 8 5 . 74 6 3 . 7 / s n ( e p o l s o ) c9 1 0 . 08 1 0 . 07 1 0 . 07 1 0 . 04 1 0 . 0 b. linear regression of t d vs. temperature at a fixed vcc: t d = slope x temperature + intercept 4. t vco = vco clock period. t pclk = pclk clock period. 5. parameters obtained from initial characterization, not subject to production testing.
188 ps7044g 06/02/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c1201 precision clock generator for laser printers vcc power-up and vco ramp to lock timing ( provided for implementation reference purposes only). pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com <-2.2ms-> 0v 5v vcc 0v 5v 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 milliseconds 0v 5v vco 0v 5v <------------ vco locked ---------->>>>> <-------- vco ramp up ---------> 2v point internal reset ~2.2v * only one bdout pulse is generated by the internal power-up reset. * timing diagram pll to output clock and beam detect reset sequence note: 1. the pclk frequency in this example is 1/4 the vco frequency (r0=0 & r1=r2=1 ? see table 1) for measurement purposes the bd# falling edge should be less than 6ns for 90% to 10%. bd# . . . vco/pll . . . . . . bdout pclk pclk bdsync . . . . . . (internal) (entering high) (entering low) t2 t3 t4 . . . t1 t6 20 22 25 t5 0 . . . 1.3v 1.5v 1.5v 12345678901234567 1 234567890123456 7 1 234567890123456 7 1 234567890123456 7 1 234567890123456 7 1 234567890123456 7 1 234567890123456 7 1 234567890123456 7 12345678901234567 12345678901234567890123456789012123456789012 1 234567890123456789012345678901212345678901 2 1 234567890123456789012345678901212345678901 2 1 234567890123456789012345678901212345678901 2 1 234567890123456789012345678901212345678901 2 1 234567890123456789012345678901212345678901 2 1 234567890123456789012345678901212345678901 2 1 234567890123456789012345678901212345678901 2 1 234567890123456789012345678901212345678901 2 1 234567890123456789012345678901212345678901 2 1 234567890123456789012345678901212345678901 2 1 234567890123456789012345678901212345678901 2 1 234567890123456789012345678901212345678901 2 1 234567890123456789012345678901212345678901 2 1 234567890123456789012345678901212345678901 2 1 234567890123456789012345678901212345678901 2 12345678901234567890123456789012123456789012
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